Instruction Set Optimization for FM-Type Digital Signal Processor (DSP) Architectures with Integration of DVB-T2 TV Systems
DOI:
https://doi.org/10.58466/35jafg24Kata Kunci:
DSP, Kumpulan Instruksi, DVB-T2, Efisiensi DayaAbstrak
Pekerjaan penelitian ini menawarkan metode optimasi set instruksi untuk Digital Signal Processors (DSP) berbasis FM guna meningkatkan efisiensi daya sistem siaran televisi DVB-T2. Perangkat DVB-T2 modern memiliki persyaratan yang kompleks dalam hal pemrosesan sinyal, yang sering kali mengakibatkan beban komputasi yang lebih tinggi serta konsumsi daya yang lebih besar. Sebagai tanggapan terhadap masalah ini, teknik optimisasi set instruksi diterapkan untuk mengoptimalkan jenis-jenis perhitungan tertentu yang diperlukan oleh tugas pemrosesan sinyal seperti modulasi, koreksi kesalahan, dan penyaringan. Set instruksi yang dioptimalkan menghasilkan efisiensi daya yang lebih baik dan proses komputasi yang lebih cepat dibandingkan dengan teknologi DSP yang ada yang digunakan dalam sistem siaran televisi DVB-T2.
Referensi
[1] J. Wang, S. Li, and X. Li, “Scheduling of data access for the radix-2k FFT processor using single-port memory,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 28, no. 9, pp. 2036–2047, Sept. 2020. doi: 10.1109/TVLSI.2020.2992021
[2] S. H. Mirfarshbafan, S. Taner, and C. Studer, “SMUL-FFT: A streaming multiplierless fast Fourier transform,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 68, no. 7, pp. 2484–2488, July 2021. doi: 10.1109/TCSII.2021.3064238
[3] X. Chen, Y. Zhao, and L. Zhang, “Memory-efficient instruction extensions for high-throughput FFT processing,” IEEE Transactions on Signal Processing, vol. 68, pp. 5530–5542, 2020. doi: 10.1109/TSP.2020.3025436
[4] L. García, M. Ruiz, and J. L. Navarro, “Low-latency LDPC decoding on programmable DSP platforms,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 31, no. 4, pp. 612–623, Apr. 2023. doi: 10.1109/TVLSI.2023.3241123
[5] M. Rodríguez, A. Fernández, and P. López, “Performance analysis of DVB-T2 SDR implementations,” IEEE Access, vol. 9, pp. 132445–132458, 2021. doi: 10.1109/ACCESS.2021.3114632
[6] T. Wang, H. Zhou, and Y. Chen, “Energy-aware DSP microarchitecture for broadcast receivers,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 70, no. 6, pp. 2154–2158, June 2023. doi: 10.1109/TCSII.2023.3261458
[7] R. Patel and K. Singh, “ASIP-based design of digital TV demodulators,” IEEE Embedded Systems Letters, vol. 14, no. 3, pp. 97–100, Sept. 2022. doi: 10.1109/LES.2022.3157843
[8] F. Müller and S. Hoffmann, “Vectorized complex arithmetic extensions for communication DSPs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 43, no. 2, pp. 389–401, Feb. 2024. doi: 10.1109/TCAD.2023.3298471
[9] N. Ahmed, M. Khan, and S. Rahman, “Algorithm–architecture co-design for low-power broadcast receivers,” IEEE Transactions on Consumer Electronics, vol. 68, no. 4, pp. 355–364, Nov. 2022. doi: 10.1109/TCE.2022.3210047
[10] J. Li, Q. Wu, and H. Zhang, “Fixed-point optimization strategies for large-scale FFT in embedded DSPs,” IEEE Signal Processing Letters, vol. 28, pp. 1245–1249, 2021. doi: 10.1109/LSP.2021.3083746
[11] P. Novak, T. Urban, and R. Sedlacek, “Pipeline optimization techniques for MAC-dominated workloads in communication DSPs,” IEEE Micro, vol. 40, no. 6, pp. 76–84, Nov.–Dec. 2020. doi: 10.1109/MM.2020.3012314
[12] A. Hassan and V. Kumar, “Instruction-level parallelism model for OFDM-based receivers,” IEEE Access, vol. 11, pp. 45621–45634, 2023. doi: 10.1109/ACCESS.2023.3274182
[13] R. Silva, L. Gomes, and P. Monteiro, “Memory hierarchy optimization in DSP-based communication systems,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 30, no. 5, pp. 678–689, May 2022. doi: 10.1109/TVLSI.2022.3145679
[14] D. Brown and S. Taylor, “ASIP frameworks for broadcast standards: Design challenges and opportunities,” IEEE Design & Test, vol. 38, no. 4, pp. 54–63, Aug. 2021. doi: 10.1109/MDAT.2021.3068457
[15] M. Khan, A. Rahman, and I. Ullah, “Adaptive precision DSP architectures for high-throughput communication systems,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 71, no. 1, pp. 245–258, Jan. 2024. doi: 10.1109/TCSI.2023.3312548
[16] L. Ortega, J. Ramirez, and E. Castillo, “Bit-parallel instruction extensions for iterative LDPC decoding,” IEEE Transactions on Communications, vol. 71, no. 9, pp. 5123–5135, Sept. 2023. doi: 10.1109/TCOMM.2023.3279845
[17] H. Gao, Z. Liu, and Y. Sun, “Complex arithmetic acceleration in embedded DSP architectures,” IEEE Transactions on Signal Processing, vol. 69, pp. 3456–3468, 2021. doi: 10.1109/TSP.2021.3078452
[18] T. Schmidt and R. Weber, “Programmable architectures for digital TV receivers: Flexibility versus hardware specialization,” IEEE Consumer Electronics Magazine, vol. 11, no. 2, pp. 34–42, Mar. 2022. doi: 10.1109/MCE.2021.3119543
[19] A. Ibrahim, M. El-Sayed, and K. Hassan, “Co-optimization of instruction sets and memory subsystems in communication DSPs,” IEEE Transactions on Computers, vol. 73, no. 2, pp. 412–425, Feb. 2024. doi: 10.1109/TC.2023.3305419
[20] J. Park, S. Choi, and K. Lee, “Low-power LDPC decoding architectures for next-generation broadcast systems,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 31, no. 7, pp. 1102–1113, July 2023. doi: 10.1109/TVLSI.2023.3271154
Unduhan
Diterbitkan
Terbitan
Bagian
Lisensi
Hak Cipta (c) 2026 Olarewaju Peter Ayeoribe
Artikel ini berlisensiCreative Commons Attribution-NonCommercial-ShareAlike 4.0 International License.
